1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus capable of amplifying charges in a photoelectric conversion area of a sensor and changing the gain of the amplification.
2. Related Background Art
An inverting amplification CMOS sensor is one of amplification photoelectric conversion apparatuses for removing noise on chip. Such a photoelectric conversion apparatus is described in, e.g., Japanese Patent Application No. 8-7329 and has an arrangement shown in FIG. 8.
Referring to FIG. 8, a photodiode 1 as a photoelectric conversion device, an amplification MOS transistor 2 for performing inverting amplification, a selection switch MOS transistor 3, and a reset MOS transistor 4 constitute a photoelectric conversion sensor cell S. A storage MOS transistor 9, an amplification MOS transistor 10, a selection switch MOS transistor 11, and a reset MOS transistor 12 form a memory cell M. One unit of a transfer system circuit is constituted by a feedback MOS switch 18 for feeding back charges to the sensor cell S, a transfer switch 19 for sending charges to the transfer circuit, a transfer switch 20 for sending charges to the memory cell M, a feedback MOS switch 21 for feeding back charges to the memory cell M, a clamp MOS switch 22, a clamp capacitor 23, and an amplification MOS transistor 24 for a source follower, and this unit is arranged for each line. This apparatus also includes a horizontal transfer MOS switch 15, an output amplifier 16, and a reset MOS transistor 17. Transmission gates 5 and 6 control pulses .phi.SL1 and .phi.PS1, respectively. Transmission gates 13 and 14 control pulses .phi.SL2 and .phi.PS2, respectively.
FIG. 9 is a drive timing chart of the photoelectric conversion apparatus. Line outputs V11 and V21 from vertical scanning circuits 1 and 2 are set at "H". At time T.sub.0, pulses .phi.RS, .phi.PS1, .phi.FT1, .phi.FT2, and .phi.PS2 are set at "H" to reset the sensor cell S, the memory cell M, and the transfer circuit. At time T.sub.1, pulses .phi.SL1 and .phi.LS are set at "H" to turn off a reset MOS transistor 7 and turn on the transmission gate 5, thereby inverting and amplifying the signal from the photodiode 1 as a sensor. The selection switch MOS transistor 3 is turned on to send the signal to the clamp capacitor 23 of the transfer circuit. Thereafter, the transfer pulse .phi.FT1 is set at "H" to turn off the transfer switch 19. The reset pulse .phi.RS is set at "H" to turn on the reset MOS transistor 17, thereby resetting the output line of the sensor cell S. At time T.sub.2, the pulses .phi.PS1 and .phi.FB1 are set at "H" to feed back the signal from the transfer circuit to the gate of the amplification MOS transistor 2 of the sensor cell S. At this time, the initial variation (noise) in the sensor cell S is removed due to the antiphase effect between the gain of the inverting amplifier 2 and that of the clamp circuit of the transfer circuit.
In this case, letting G.sub.S be the inverting amplification gain, G.sub.T be the clamp circuit gain, and N.sub.init be the initial noise, noise N after the feedback operation is given by: EQU N=N.sub.init (1+G.sub.S .times.G.sub.T)
The inverting amplification gain that minimizes noise is given by G.sub.S =-1/G.sub.T. When the clamp gain is 0.98, the inverting amplification gain can be -1/0.98=-1.02.
At time T.sub.3, the signal is sent from the sensor cell S to the transfer circuit again and clamped. At time T.sub.4, pulses .phi.FB2 and .phi.PS2 are set at "H" to write a voltage proportional to charges held by the clamp capacitor 23 in the memory cell M.
The above operation is performed for all lines while performing vertical scanning, thereby completing the reset operation. After an arbitrary storage time, the signal is read out from the sensor cell S. At time T.sub.5, the pulse .phi.SL1 is set at "H" to invert and amplify the signal and read out the signal from the sensor cell S. At time T.sub.6, the pulse .phi.SL2 is set at "H" to read out an initial signal stored in the memory cell M and obtain a voltage difference from the sensor signal. At time T.sub.7, the voltage difference is written in the memory cell M. After that, the horizontal scanning circuit performs scanning and outputs the signal to the vertical output terminal through the amplifier 16. Finally, the noise N becomes: EQU N=N.sub.init (1+G.sub.M .times.G.sub.T)
When the inverting gain of the memory unit is G.sub.M =-1/G.sub.T, the noise is minimized. The gain of the inverting amplifier 10 depends on the ratio of a conductance gm of the amplification MOS transistor 10 to a conductance gm' of the load MOS transistor 11. For this reason, when a gate length L or a gate width W of a load MOS transistor 8 is changed to change the conductance gm', the inverting amplification gain can be set to minimize the noise component. This applies not only to noise reduction by the load MOS transistor 8 of the memory cell M but also to noise reduction by the load MOS transistor 7 of the sensor cell S.
However, in the above-described photoelectric conversion apparatus, small variations in well concentration, oxide film thickness, or processing size among lots, wafers, or chips may change the conductance gm of the MOS transistor, resulting in deviation of the inverting amplification gain from its optimum value. If the gain deviates from the optimum value, the noise correction effect degrades, and the output variation among cells, i.e., so-called FPN (Fixed Pattern Noise) increases. This may increase the ratio of defective chips having noise larger than the prescribed value to result in a low yield.